ZPUino Release Notes
Here you can read the release notes for the following releases:
- ZPUino 1.0 Release (2012/04/10)
- ZPUino Beta 2 Release (2011/07/19)
- ZPUino Beta 1 Release (2011/06/21)
- ZPUino Alpha 4 Release (2011/04/25)
- ZPUino Alpha 3 Release (2011/04/08)
- ZPUino Alpha 2 Release (2011/03/06)
This release is a major release!. Many many changes were done to all components, and not all of them are depicted here. Please refer to git changelogs for more detail.
- New ZPU core - ZPU Extreme!.
- Most cores are now Wishbone compatible.
- New timer implementation
- All IO devices were pushed to the top level module, to ease customization
- New IDE based on Arduino 1.0
- Upload-to-RAM feature (control-click on Upload button!!!)
- Code is now smaller due to new toolchain features
- Some common functions are now exported by the bootloader, to reduce code size.
- Some functions have now assembly implementations for speed.
- New board: Papilio Plus S6LX4
- New board: Papilio Plus S6LX9
- New board: Nexys2 S3E1200 (thanks to Paul Urbanus)
- New board variants!
- Small fixes here and then.
- SID HDL implementation
- Pokey HDL implementation
- YM2149 HDL implementation
- Audiomixer and simple sigmadelta
- OpenCores I2C
This release focus on bug fixing, some new devices and timing issues. Also the simulator was greatly improved.
- Added some pipelining on arithmetic instructions, this helps meet timing and does not impact performance
- A new device is under test, which is a YM2149 audio chip. Thanks to fpgaarcade and Shazz^TRSI for it. The device is only included in the VGA-capable releases, since it's used mostly in games.
- Fixed the mksmallfs.exe binary on WIN32, which might fail if some scenarios.
- Fixed some Papilio One pin mappings, and added proper WING_B defines
- VGA: fixed text positioning
- Finally Win32 support!.
- The system is now Wishbone compatible. Although the core itself is not 100% Wishbone compliant, the IO module is, thus any wishbone device connected to the IO module should work.
- Some minor changes to reset operation. Should perform better now.
- There have been reports of serial problems with some USB-to-serial adapters (prolific). If you encounter any problem let us know.
- The sketches and bootloader now include a board identification. This will prevent running programs built for a board other than the implemented.
- The sketches now can access some bootloader data.
- The IO address space was greatly increased. See the board definition files for details.
- A new IO device was added: a HQVGA (160x120) adaptor, with 8-bit color (3 bits red, 3 bits green, 2 bits blue). This requires at least a S3E500 because it uses a lot of memory.
- The core now implements right shifts in hardware.
- The core now implements multiplication in hardware.
- Fixed SPI offset for S3E500
- A new image was added for P1 500, with a VGA core
Spartan 3E Evaluation Board
- A new image was added for S3ESK500, with a VGA core. This core maps 8-bit into 3 due to board VGA limitations.
- The IDE was updated with new board IDs.
- A new library is available: SmallFS. See this link for more details.
- A new VGA library is available to work with the new VGA core.
- Changed the reset method to BREAK + low speed transfer. This hopefully will allow reset even when RS232 signals are noisy.
- Fix bootloader for simulation, was using deprecated methods.
- Small update for new interrupt controller
- Remove unused syscall file for bootloader
- Refactor interrupt controller. New controller uses edge interrupts, and has two external interrupt lines. Also interrupts are now masked by default.
- GPIO: allow disabling PPS on some GPIO pins, such as those who map directly on board devices.
- Clock speed was being defined as unsigned long long. This might break inline computations, so changed to unsigned long.
- Place memreg in lower memory, so it can be used by bootloader/sketch. Interrupts should work perfectly now (and sketches should be slightly smaller)
- Reorganize papilio one directory to hold different FPGA
- New bitfile for Papilio One based on S3E500
Spartan 3E Evaluation Board
- Add some more IO pins to design, to support accessing LCD and rotary encoder.
- A small demo is now on the examples area
- Programmer now uses a dual-speed transfer. It starts at 115200 baud for identification, then ramps up speed if required.
- Some bugfixes and refactoring.
- Preliminary direct memory upload. Still untested.
- New main ZPU core: ZPU Premium. You should expect almost a 3x performance increase, when compared with old core.
- New PPS implementation. Things should have become clearer now. See more information on PPS page
- IO selection is now clearer, so to ease adding new devices. See Implementing or porting IO devices document for more information
- Fixed RAM indexing, which caused synthesis warnings
- Added per-board SPI clock dividers for bootloader
Spartan 3E Evaluation Board
- First prebuilt image for this board
- Design was not being properly built, fixed that.
- Changed clock speed to 96MHz, instead of 100MHz. This helps meeting timing and give accurate baud rate dividers
- Fixed GPIO mappings
- Added proper IO pads
- Added IO device tutorial: Implementing or porting IO devices
- Added Advanced IO: Advanced IO
- Added PPS documentation for users: Peripheral Pin Select
- There is still no Win32 port. Some dificculties arose so I'm delaying to next release. But good news is that compiler is now built, but other parts of the toolchain still need some tweaking, as well as the IDE set up.
- Resetting the serial port sometimes fails when using a real RS232 cable. This is probably due to ringing - I'll address this on next release (this only affects S3E evaluation board, but since there's a manual reset button you can get it to work)
- S3E P&R is having difficulties due to both DCM used, but it does meet timing. However I'll address that on next release, to speed up the implementation process.
- Added sketch size and CRC to programmer. This will prevent bootloader from loading unknown or corrupted sketches.
- Preliminary WIN32 support.
- Programmer is now released under GPLv3.
- Added minus-one and minus-two CRC16 values. This allows user to fetch CRC16 outputs from previous updates, very useful when you're using a frame and CRC is the last frame value.
- Add second channel Sigma Delta DAC.
- Added little-endian support, and delayed set.
- New UART receive module. This new unit uses 16x oversampling, and a majority voting filter.
- Fixed a nasty bug that caused RAM to be not properly infered (write-first mode was not being selected), thus invalidating the whole design.
- Added proper input pads (latches+FF's).
SPI ADC support
- Added preliminary ADC sampler support, with 16Kbit receive buffer
- Arduino's SD library now works with ZPUino, but in read-only mode, due to code size issues.
- SPI module should use proper CPOL/CPHA. This is still under development.
- Most Arduino libaries were not yet ported.